1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for selecting wafer alignment marks based on film thickness variation.
2. Description of the Related Art
During the manufacture of semiconductor devices, semiconductor wafers, each including a plurality of individual die, are subjected to a number of processing steps. Typically, wafers are grouped into lots that are processed together. Each lot may contain, for example, 25 individual wafers. Certain of the processing steps are sensitive to the alignment of the wafer within the processing tool. For example, photolithography processing steps are highly sensitive to the alignment of the wafer. Other steps, including metrology steps, are also sensitive to wafer alignment, but to differing degrees.
FIG. 1 illustrates a typical semiconductor wafer 100. The wafer 100 includes an orientation notch 110 useful as a reference point for a rough alignment of the wafer 100. For identification purposes, a unique wafer identification code 120 is scribed on the wafer 100 beneath the notch 110 using a laser scribing process where small dots are burned into the surface of the wafer to construct the characters or symbols of the code. Exemplary wafer identification codes 120 may include alphanumeric identifiers or bar code identifiers (e.g., 1 or 2 dimensional codes). During the production process, process history and metrology information is stored in a database for each of the wafers 100 indexed by its respective wafer identification code 120.
Typically, prior to performing an orientation-sensitive process, the wafer 100 is rotated until the notch 110 is located and placed in a predetermined position. Other techniques for performing rough alignments include using an edge alignment procedure where the wafer 100 is rotated and optically scanned to determine the profile of the edge at various positions about the rotation. Typically, a wafer 100 is not perfectly round. As such, the edge moves with respect to a fixed reference point as the wafer 100 is rotated. By determining the edge profile, the approximate center of the wafer 100 can be determined. The spatial relationship between the notch 110 and the approximate center point may be then used as a reference point for rough alignment of the wafer.
These rough alignment techniques are not suitable for highly sensitive processes such as photolithography. Accordingly, multiple sets of alignment marks 130, 135, 140 are etched into the wafer 100 near the periphery prior to the commencement of process steps for forming devices on the wafer 100. A wafer 100 typically includes a plurality of individual semiconductor die 150 arranged in a grid 155. Photolithography steps are typically performed by a stepper on approximately one to four die locations at a time, depending on the specific photomask employed. The alignment marks 130, 135, 140 provide an accurate reference point for aligning the stepper to the individual cells in the grid 155 that are to be exposed. The stepper includes sensitive optical scanning equipment to locate the alignment marks 130, 135, 140 and finely align the wafer 100 based on the alignment marks 130, 135, 140 such that the individual die 150 are accurately patterned.
Typically, the stepper selects one of the sets of alignment marks 130, 135, 140 for alignment. Although only three sets of alignment marks 130, 135, 140 are shown, more sets may be possible. The different sets of alignment marks 130, 135, 140 are disposed at different distances from the edge of the wafer 100. For example, the alignment marks 130, 135 may be disposed about 4 nm from the edge and the alignment marks 140 may be disposed 5 nm from the edge. Because of the different positions of the alignment marks 130, 135, 140, they are not subject to the exact same processing environment. Accordingly, the ability of the stepper to align to one set of alignment marks 130, 135, 140 may differ from its ability to align to the other set of alignment marks 130, 135, 140. If one particular set of alignment marks 130, 135, 140 is damaged by processing, resulting in a lower signal to noise ratio in the alignment process, the stepper may use an alternative set of alignment marks 130, 135, 140 having a higher signal to noise ratio.
Generally, the stepper selects one set of the alignment marks 130, 135, 140 as a default set, aligns the wafer 100 using the selected set of alignment marks 130, 135, 140, and exposes a layer of photoresist material to form a desired pattern. If the set of alignment marks 130, 135, 140 chosen had a relatively low signal to noise ratio, the alignment may be incorrect. In some cases alignment errors may be detected, and the wafer 100 may be reworked. During the rework, a different set of alignment marks 130, 135, 140 is selected by the stepper to align the wafer 100. In other cases, the alignment error is not detected until after a process that may not be reversed has been performed (e.g., etching). In such as case, the wafer 100 must be scrapped. Reworking or the scrapping the wafer is expensive and reduces the efficiency of the processing line.
As seen in FIG. 2A, an illustrative grating structure 200 used to define the alignment marks 130, 135, 140 is shown. The grating structure 200 includes trenches 210 formed in a silicon substrate 220, shown in cross-section in FIGS. 2B and 2C. A variety of different constructs for the grating structure 200 may be used. For example, an alternate grating structure may comprise a single, rectangular group of trenches.
As shown in FIG. 2B, during the fabrication of shallow trench isolation (STI) structures on the wafer 100, a layer of silicon nitride 230 is deposited on the wafer 100 for use as a stop layer for chemical mechanical polishing. A layer of silicon dioxide 240 formed using tetraethoxysilane (TEOS) is formed over the silicon nitride 230 (i.e., other layers, such as a silicon oxynitride antireflective coating layer (ARC) (not shown) and a liner oxide layer (not shown) may be disposed between the silicon nitride stop layer 230 and the silicon dioxide layer 240), The silicon nitride stop layer 230 is deposited over the entire wafer 100, including over the grating structure 200. The silicon dioxide layer 240 is subsequently polished to remove excess material, and the silicon nitride stop layer 230 is stripped.
Typical CMP polishing processes do not tightly control the polish rates near the edges of the wafer 100 (i.e., where the alignment marks 130, 135, 140 are located), because no devices are present in that region and also because there are no available metrology techniques for monitoring the polishing rates near the edges. Accordingly, the edge regions may be overpolished or underpolished with respect to the other portions of the wafer 100. If the edge region is over polished, all of the silicon nitride stop layer 230 is polished away and a portion of the silicon substrate 220 in which the trenches 210 are formed is also removed. If a portion of the edge region is underpolished, remnants of the silicon oxide layer 240 may remain over the trenches 220 and interfere with the subsequent stripping of the nitride stop layer 230. As seen in FIG. 2C, in an overpolished region 250, the depth of the trenches 210 is reduced. In an underpolished region 260, remnants of the silicon nitride stop layer 230 remain in the bottom of the trenches 210.
The remnants of the silicon nitride stop layer 230 result in a degradation of the signal to noise ratio when the alignment marks 130, 135, 140 are used for subsequent optical alignment. In some of the trenches 210, no remnants may be present (i.e., no underpolishing). For the trenches 210, with silicon nitride remnants 220, the amount of remaining silicon nitride typically follows an increasing or decreasing trend as the distance from the edge of the wafer 100 increases in accordance with the surface gradient caused by the polishing variation.
Because of the variation caused by the overpolishing or underpolishing, it is difficult to predict which set of alignment marks 130, 135, 140 will have a higher signal to noise ratio. For example, some wafers may be uniformly underpolished or overpolished, some wafers may be overpolished nearer the edge and underpolished further from the edge (i.e., as shown in FIG. 2C), and still other wafers may be underpolished nearer the edge and overpolished further from the edge.
Polishing variation may also be present in processing steps directed to forming other structures on the wafer 100. This variation can have a similar degrading effect on the alignment marks 130, 135, 140. For example, certain metal layers subsequently formed on the wafer 100 are polished. Polishing variation in the region where the alignment marks are located may also result in remnants of other process layer being deposited in the trenches 210 of the grating structure 200 used to define the alignment marks 130, 135, 140.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a method for aligning wafers. The method includes providing a wafer having at least a first and a second alignment mark formed thereon, each alignment mark comprising a grating structure; illuminating the grating structure of the first alignment mark with a light source; measuring light reflected from the grating structure of the first alignment mark to generate a first reflection profile; illuminating the grating structure of the second alignment mark with the light source; measuring light reflected from the grating structure of the second alignment mark to generate a second reflection profile; and selecting one of the first and second alignment marks for aligning the wafer based on the first and second reflection profiles.
Another aspect of the present invention is seen in a processing line including a metrology tool and a process controller. The metrology tool is adapted to receive a wafer having at least a first and a second alignment mark formed thereon. Each alignment mark comprises a grating structure. The metrology tool is further adapted to illuminate the grating structure of the first alignment mark with a light source, measure light reflected from the grating structure of the first alignment mark to generate a first reflection profile, illuminate the grating structure of the second alignment mark with the light source, and measure light reflected from the grating structure of the second alignment mark to generate a second reflection profile. The process controller is adapted to select one of the first and second alignment marks for aligning the wafer based on the first and second reflection profiles.